Taipei, March 31 (CNA) Taiwan Semiconductor Manufacturing Co. (TSMC) received government approval on Tuesday to deploy its advanced 3-nanometer (3nm) process at its second fab currently under construction in Japan, according to a news release.
The Ministry of Economic Affairs (MOEA) green-lit the plan for the facility in Kumamoto, which is scheduled to start installing equipment and come online in 2028 with a monthly production capacity of 15,000 12-inch wafers, the ministry said in the release.
The MOEA's Department of Investment Review in June 2024 authorized a US$5.26 billion investment for the facility, slated to manufacture 6- to 12nm chips, significantly less advanced than 3nm process.
At a meeting with Japanese Prime Minister Sanae Takaichi in Tokyo this February, TSMC CEO C.C. Wei (魏哲家) had stated that the shift in plan for the second fab was a response to soaring global demand for artificial intelligence.
TSMC's first Kumamoto fab, operated by Japan Advanced Semiconductor Manufacturing, Inc. (JASM), entered mass production in late 2024, primarily focusing on 12nm-28nm logic chips for the automotive and industrial sectors.
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